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Rev Log message Author Age Path
113 RxPointer bug fixed. mohor 7008d 09h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7008d 22h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 7009d 12h /
110 m_wb_cyc_o signal released after every single transfer. mohor 7009d 15h /
109 Comment removed. mohor 7009d 15h /
108 Testbench supports unaligned accesses. mohor 7077d 01h /
107 TX_BUF_BASE changed. mohor 7077d 01h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7077d 01h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7086d 03h /
104 FCS should not be included in NibbleMinFl. mohor 7087d 21h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7087d 21h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 7087d 22h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 7087d 22h /
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 7087d 22h /
99 Document revised. mohor 7094d 21h /
98 Document revised. mohor 7094d 21h /
97 Small typo fixed. lampret 7111d 19h /
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.
mohor 7115d 19h /
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.
mohor 7115d 22h /
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.
mohor 7115d 22h /

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