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Rev Log message Author Age Path
118 ShiftEnded synchronization changed. mohor 6348d 15h /
117 Clock mrx_clk set to 2.5 MHz. mohor 6349d 01h /
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 6349d 01h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 6349d 23h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 6350d 20h /
113 RxPointer bug fixed. mohor 6357d 12h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 6358d 02h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 6358d 15h /
110 m_wb_cyc_o signal released after every single transfer. mohor 6358d 18h /
109 Comment removed. mohor 6358d 19h /
108 Testbench supports unaligned accesses. mohor 6426d 05h /
107 TX_BUF_BASE changed. mohor 6426d 05h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 6426d 05h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 6435d 06h /
104 FCS should not be included in NibbleMinFl. mohor 6437d 00h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 6437d 01h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 6437d 01h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 6437d 01h /
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 6437d 01h /
99 Document revised. mohor 6444d 00h /

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