OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 118

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
118 ShiftEnded synchronization changed. mohor 7551d 04h /
117 Clock mrx_clk set to 2.5 MHz. mohor 7551d 15h /
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7551d 15h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7552d 12h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7553d 10h /
113 RxPointer bug fixed. mohor 7560d 02h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7560d 15h /
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7561d 05h /
110 m_wb_cyc_o signal released after every single transfer. mohor 7561d 08h /
109 Comment removed. mohor 7561d 08h /
108 Testbench supports unaligned accesses. mohor 7628d 18h /
107 TX_BUF_BASE changed. mohor 7628d 18h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7628d 18h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 7637d 20h /
104 FCS should not be included in NibbleMinFl. mohor 7639d 14h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 7639d 14h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 7639d 15h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 7639d 15h /
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 7639d 15h /
99 Document revised. mohor 7646d 14h /
98 Document revised. mohor 7646d 14h /
97 Small typo fixed. lampret 7663d 12h /
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 7667d 12h /
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 7667d 15h /
94 When clear and read/write are active at the same time, cnt and pointers are
set to 1.		 mohor 7667d 15h /
93 When in promiscous mode some frames were not received correctly. Fixed. mohor 7672d 13h /
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 7673d 16h /
91 Comments in Slovene language removed. mohor 7673d 16h /
90 casex changed with case, fifo reset changed. mohor 7673d 16h /
89 TX_BD_NUM, MAC_ADDR0 and MAC_ADDR1 register description
changed.		 mohor 7677d 14h /

powered by: WebSVN 2.1.0

© copyright 1999-2023 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.