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Rev Log message Author Age Path
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7803d 05h /
118 ShiftEnded synchronization changed. mohor 7806d 19h /
117 Clock mrx_clk set to 2.5 MHz. mohor 7807d 06h /
116 Testing environment also includes traffic cop, memory interface and host
mohor 7807d 06h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7808d 04h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7809d 01h /
113 RxPointer bug fixed. mohor 7815d 17h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7816d 07h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 7816d 20h /
110 m_wb_cyc_o signal released after every single transfer. mohor 7816d 23h /
109 Comment removed. mohor 7817d 00h /
108 Testbench supports unaligned accesses. mohor 7884d 10h /
107 TX_BUF_BASE changed. mohor 7884d 10h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7884d 10h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7893d 11h /
104 FCS should not be included in NibbleMinFl. mohor 7895d 05h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7895d 06h /
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.
mohor 7895d 06h /
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 7895d 06h /
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).
mohor 7895d 06h /

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