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Rev Log message Author Age Path
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7803d 05h /
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7803d 05h /
120 Unused files removed. mohor 7803d 06h /
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7803d 06h /
118 ShiftEnded synchronization changed. mohor 7806d 20h /
117 Clock mrx_clk set to 2.5 MHz. mohor 7807d 07h /
116 Testing environment also includes traffic cop, memory interface and host
mohor 7807d 07h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7808d 05h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7809d 02h /
113 RxPointer bug fixed. mohor 7815d 18h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7816d 08h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 7816d 21h /
110 m_wb_cyc_o signal released after every single transfer. mohor 7817d 00h /
109 Comment removed. mohor 7817d 01h /
108 Testbench supports unaligned accesses. mohor 7884d 11h /
107 TX_BUF_BASE changed. mohor 7884d 11h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7884d 11h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7893d 12h /
104 FCS should not be included in NibbleMinFl. mohor 7895d 06h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v
mohor 7895d 07h /

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