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Rev	Log message	Author	Age	Path
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7946d 05h	/
126	InvalidSymbol generation changed.	mohor	7946d 05h	/
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7946d 05h	/
124	Define ETH_MIIMODER_RST corrected to 0x00000400.	mohor	7946d 06h	/
123	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7948d 06h	/
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7948d 06h	/
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	7948d 06h	/
120	Unused files removed.	mohor	7948d 08h	/
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7948d 08h	/
118	ShiftEnded synchronization changed.	mohor	7951d 22h	/
117	Clock mrx_clk set to 2.5 MHz.	mohor	7952d 09h	/
116	Testing environment also includes traffic cop, memory interface and host interface.	mohor	7952d 09h	/
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7953d 07h	/
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7954d 04h	/
113	RxPointer bug fixed.	mohor	7960d 20h	/
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7961d 10h	/
111	Master state machine had a bug when switching from master write to master read.	mohor	7961d 23h	/
110	m_wb_cyc_o signal released after every single transfer.	mohor	7962d 02h	/
109	Comment removed.	mohor	7962d 03h	/
108	Testbench supports unaligned accesses.	mohor	8029d 13h	/
107	TX_BUF_BASE changed.	mohor	8029d 13h	/
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8029d 13h	/
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8038d 14h	/
104	FCS should not be included in NibbleMinFl.	mohor	8040d 08h	/
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8040d 09h	/
102	Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled or not.	mohor	8040d 09h	/
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8040d 09h	/
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8040d 09h	/
99	Document revised.	mohor	8047d 08h	/
98	Document revised.	mohor	8047d 08h	/

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