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Rev Log message Author Age Path
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 7054d 04h /
128 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7074d 03h /
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7074d 03h /
126 InvalidSymbol generation changed. mohor 7074d 03h /
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 7074d 03h /
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7074d 04h /
123 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7076d 05h /
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7076d 05h /
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7076d 05h /
120 Unused files removed. mohor 7076d 06h /
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7076d 06h /
118 ShiftEnded synchronization changed. mohor 7079d 21h /
117 Clock mrx_clk set to 2.5 MHz. mohor 7080d 08h /
116 Testing environment also includes traffic cop, memory interface and host
mohor 7080d 08h /
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7081d 06h /
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7082d 03h /
113 RxPointer bug fixed. mohor 7088d 19h /
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7089d 09h /
111 Master state machine had a bug when switching from master write to
master read.
mohor 7089d 22h /
110 m_wb_cyc_o signal released after every single transfer. mohor 7090d 01h /

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