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Rev Log message Author Age Path
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7965d 09h /
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7965d 22h /
110 m_wb_cyc_o signal released after every single transfer. mohor 7966d 01h /
109 Comment removed. mohor 7966d 02h /
108 Testbench supports unaligned accesses. mohor 8033d 11h /
107 TX_BUF_BASE changed. mohor 8033d 11h /
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8033d 12h /
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8042d 13h /
104 FCS should not be included in NibbleMinFl. mohor 8044d 07h /
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8044d 08h /

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