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Rev	Log message	Author	Age	Path
146	CarrierSenseLost status is not set when working in loopback mode.	mohor	7904d 12h	/
145	Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).	mohor	7904d 12h	/
144	This commit was manufactured by cvs2svn to create tag 'runing_under_uclinux'.		7920d 14h	/
143	Only values smaller or equal to 0x80 can be written to TX_BD_NUM register. r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.	mohor	7920d 14h	/
142	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7923d 08h	/
141	Syntax error fixed.	mohor	7923d 08h	/
140	Syntax error fixed.	mohor	7923d 08h	/
139	Synchronous reset added to all registers. Defines used for width. r_MiiMRst changed from bit position 10 to 9.	mohor	7923d 08h	/
138	Synchronous reset added.	mohor	7923d 08h	/
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	7923d 08h	/
136	Parameter ResetValue changed to capital letters.	mohor	7923d 18h	/
135	New revision. External DMA removed, TX_BD_NUM changed.	mohor	7925d 10h	/
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7925d 11h	/
133	- Busy signal was not set on time when scan status operation was performed and clock was divided with more than 2. - Nvalid remains valid two more clocks (was previously cleared too soon).	mohor	7925d 12h	/
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	7925d 12h	/
131	LinkFail signal was not latching appropriate bit.	mohor	7925d 12h	/
130	First draft of the Ethernet design document. Not a finished version. Still many things missing.	mohor	7925d 12h	/
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	7925d 13h	/
128	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7945d 12h	/
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7945d 12h	/
126	InvalidSymbol generation changed.	mohor	7945d 12h	/
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7945d 12h	/
124	Define ETH_MIIMODER_RST corrected to 0x00000400.	mohor	7945d 13h	/
123	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7947d 14h	/
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7947d 14h	/
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	7947d 14h	/
120	Unused files removed.	mohor	7947d 15h	/
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7947d 15h	/
118	ShiftEnded synchronization changed.	mohor	7951d 06h	/
117	Clock mrx_clk set to 2.5 MHz.	mohor	7951d 16h	/

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