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Rev Log message Author Age Path
162 Another temporary version. Core is almost finished. Testbench not included,
yet.
mohor 7900d 05h /
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7900d 10h /
160 error acknowledge cycle termination added to display. mohor 7900d 10h /
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7901d 07h /
158 Typo fixed. mohor 7901d 07h /
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7903d 12h /
156 Valid testbench. mohor 7903d 12h /
155 Minor changes. mohor 7903d 12h /
154 Design document is still under construction. mohor 7904d 11h /
153 Temp version (backup). mohor 7905d 03h /

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