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Rev Log message Author Age Path
216 Bist signals added. mohor 6671d 21h /
215 Bist supported. mohor 6671d 22h /
214 Signals for WISHBONE B3 compliant interface added. mohor 6672d 18h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6672d 18h /
212 Minor $display change. mohor 6672d 18h /
211 Bist added. mohor 6672d 18h /
210 BIST added. mohor 6672d 18h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6673d 22h /
208 Virtual Silicon RAMs moved to lib directory tadej 6689d 16h /
207 Virtual Silicon RAM support fixed tadej 6689d 16h /
206 Virtual Silicon RAM added to the simulation. mohor 6689d 16h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 6689d 16h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 6689d 17h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 6689d 17h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 6692d 18h /
201 Core size added to the document. mohor 6692d 19h /
200 File with lower case checked in instead. mohor 6692d 19h /
199 Datasheet name changed to lower case name. mohor 6692d 19h /
198 Removed file. File with name in lower case will be added instead. mohor 6692d 19h /
197 Ethernet Data Sheet. mohor 6692d 19h /

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