Subversion Repositories ethmac

[/] - Rev 219


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7863d 21h /
218 Typo error fixed. (When using Bist) mohor 7863d 23h /
217 Bist supported. mohor 7863d 23h /
216 Bist signals added. mohor 7863d 23h /
215 Bist supported. mohor 7864d 00h /
214 Signals for WISHBONE B3 compliant interface added. mohor 7864d 20h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7864d 20h /
212 Minor $display change. mohor 7864d 20h /
211 Bist added. mohor 7864d 20h /
210 BIST added. mohor 7864d 20h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7865d 23h /
208 Virtual Silicon RAMs moved to lib directory tadej 7881d 17h /
207 Virtual Silicon RAM support fixed tadej 7881d 17h /
206 Virtual Silicon RAM added to the simulation. mohor 7881d 17h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7881d 18h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7881d 18h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 7881d 18h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7884d 19h /
201 Core size added to the document. mohor 7884d 20h /
200 File with lower case checked in instead. mohor 7884d 20h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.