Subversion Repositories ethmac

[/] - Rev 220


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7898d 11h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7898d 11h /
218 Typo error fixed. (When using Bist) mohor 7898d 13h /
217 Bist supported. mohor 7898d 13h /
216 Bist signals added. mohor 7898d 13h /
215 Bist supported. mohor 7898d 13h /
214 Signals for WISHBONE B3 compliant interface added. mohor 7899d 09h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7899d 09h /
212 Minor $display change. mohor 7899d 09h /
211 Bist added. mohor 7899d 10h /
210 BIST added. mohor 7899d 10h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7900d 13h /
208 Virtual Silicon RAMs moved to lib directory tadej 7916d 07h /
207 Virtual Silicon RAM support fixed tadej 7916d 07h /
206 Virtual Silicon RAM added to the simulation. mohor 7916d 07h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7916d 08h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7916d 08h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 7916d 08h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7919d 09h /
201 Core size added to the document. mohor 7919d 10h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.