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220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7925d 03h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7925d 03h /
218 Typo error fixed. (When using Bist) mohor 7925d 05h /
217 Bist supported. mohor 7925d 05h /
216 Bist signals added. mohor 7925d 05h /
215 Bist supported. mohor 7925d 06h /
214 Signals for WISHBONE B3 compliant interface added. mohor 7926d 01h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7926d 02h /
212 Minor $display change. mohor 7926d 02h /
211 Bist added. mohor 7926d 02h /
210 BIST added. mohor 7926d 02h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7927d 05h /
208 Virtual Silicon RAMs moved to lib directory tadej 7942d 23h /
207 Virtual Silicon RAM support fixed tadej 7942d 23h /
206 Virtual Silicon RAM added to the simulation. mohor 7942d 23h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7943d 00h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7943d 00h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 7943d 00h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7946d 01h /
201 Core size added to the document. mohor 7946d 02h /
200 File with lower case checked in instead. mohor 7946d 02h /
199 Datasheet name changed to lower case name. mohor 7946d 02h /
198 Removed file. File with name in lower case will be added instead. mohor 7946d 02h /
197 Ethernet Data Sheet. mohor 7946d 02h /
196 Ethernet product brief. mohor 7946d 03h /
195 Product brief removed because it is the same as Datasheet. mohor 7946d 03h /
194 Full duplex tests modified and testbench bug repaired. tadej 7946d 04h /
193 Temp version (backup). mohor 7946d 06h /
192 Some additional reports added tadej 7948d 00h /
191 Bug repaired in eth_phy device tadej 7948d 00h /

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