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Rev Log message Author Age Path
224 Signals for a wave window in Modelsim. tadejm 7856d 21h /
223 Some code changed due to bug fixes. tadejm 7856d 21h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7860d 19h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7860d 19h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7863d 20h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7863d 20h /
218 Typo error fixed. (When using Bist) mohor 7863d 22h /
217 Bist supported. mohor 7863d 22h /
216 Bist signals added. mohor 7863d 22h /
215 Bist supported. mohor 7863d 23h /
214 Signals for WISHBONE B3 compliant interface added. mohor 7864d 18h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7864d 19h /
212 Minor $display change. mohor 7864d 19h /
211 Bist added. mohor 7864d 19h /
210 BIST added. mohor 7864d 19h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7865d 22h /
208 Virtual Silicon RAMs moved to lib directory tadej 7881d 16h /
207 Virtual Silicon RAM support fixed tadej 7881d 16h /
206 Virtual Silicon RAM added to the simulation. mohor 7881d 16h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7881d 17h /

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