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Rev Log message Author Age Path
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7038d 12h /
225 Some minor changes. tadejm 7038d 12h /
224 Signals for a wave window in Modelsim. tadejm 7038d 13h /
223 Some code changed due to bug fixes. tadejm 7038d 14h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7042d 12h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7042d 12h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7045d 12h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7045d 12h /
218 Typo error fixed. (When using Bist) mohor 7045d 14h /
217 Bist supported. mohor 7045d 14h /
216 Bist signals added. mohor 7045d 14h /
215 Bist supported. mohor 7045d 15h /
214 Signals for WISHBONE B3 compliant interface added. mohor 7046d 11h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7046d 11h /
212 Minor $display change. mohor 7046d 11h /
211 Bist added. mohor 7046d 11h /
210 BIST added. mohor 7046d 11h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7047d 14h /
208 Virtual Silicon RAMs moved to lib directory tadej 7063d 08h /
207 Virtual Silicon RAM support fixed tadej 7063d 08h /

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