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Rev Log message Author Age Path
231 Description of Core Modules added (figure). mohor 6979d 01h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6982d 21h /
229 case changed to casex. mohor 6982d 21h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6983d 01h /
227 Changed BIST scan signals. tadejm 6983d 01h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6983d 03h /
225 Some minor changes. tadejm 6983d 03h /
224 Signals for a wave window in Modelsim. tadejm 6983d 04h /
223 Some code changed due to bug fixes. tadejm 6983d 04h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 6987d 02h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6987d 02h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6990d 03h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 6990d 03h /
218 Typo error fixed. (When using Bist) mohor 6990d 05h /
217 Bist supported. mohor 6990d 05h /
216 Bist signals added. mohor 6990d 05h /
215 Bist supported. mohor 6990d 06h /
214 Signals for WISHBONE B3 compliant interface added. mohor 6991d 02h /
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6991d 02h /
212 Minor $display change. mohor 6991d 02h /
211 Bist added. mohor 6991d 02h /
210 BIST added. mohor 6991d 02h /
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6992d 05h /
208 Virtual Silicon RAMs moved to lib directory tadej 7007d 23h /
207 Virtual Silicon RAM support fixed tadej 7007d 23h /
206 Virtual Silicon RAM added to the simulation. mohor 7007d 23h /
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7008d 00h /
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7008d 00h /
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 7008d 00h /
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7011d 01h /

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