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Rev Log message Author Age Path
233 Revision 0.3 released. Some figures added. mohor 6566d 12h /
232 fpga define added. mohor 6571d 07h /
231 Description of Core Modules added (figure). mohor 6573d 08h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6577d 05h /
229 case changed to casex. mohor 6577d 05h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6577d 09h /
227 Changed BIST scan signals. tadejm 6577d 09h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6577d 10h /
225 Some minor changes. tadejm 6577d 10h /
224 Signals for a wave window in Modelsim. tadejm 6577d 12h /
223 Some code changed due to bug fixes. tadejm 6577d 12h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 6581d 10h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6581d 10h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6584d 10h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6584d 10h /
218 Typo error fixed. (When using Bist) mohor 6584d 12h /
217 Bist supported. mohor 6584d 12h /
216 Bist signals added. mohor 6584d 12h /
215 Bist supported. mohor 6584d 13h /
214 Signals for WISHBONE B3 compliant interface added. mohor 6585d 09h /

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