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Rev	Log message	Author	Age	Path
238	Defines fixed to use generic RAM by default.	mohor	7993d 05h	/
237	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7995d 11h	/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7995d 11h	/
235	rev 4.	mohor	7996d 01h	/
234	Figure list assed to the revision 3.	mohor	7996d 10h	/
233	Revision 0.3 released. Some figures added.	mohor	7996d 10h	/
232	fpga define added.	mohor	8001d 05h	/
231	Description of Core Modules added (figure).	mohor	8003d 06h	/
230	This commit was manufactured by cvs2svn to create tag 'rel_8'.		8007d 03h	/
229	case changed to casex.	mohor	8007d 03h	/
228	This commit was manufactured by cvs2svn to create tag 'rel_7'.		8007d 07h	/
227	Changed BIST scan signals.	tadejm	8007d 07h	/
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	8007d 08h	/
225	Some minor changes.	tadejm	8007d 08h	/
224	Signals for a wave window in Modelsim.	tadejm	8007d 10h	/
223	Some code changed due to bug fixes.	tadejm	8007d 10h	/
222	This commit was manufactured by cvs2svn to create tag 'rel_6'.		8011d 08h	/
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	8011d 08h	/
220	This commit was manufactured by cvs2svn to create tag 'rel_5'.		8014d 08h	/
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	8014d 08h	/

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[/] - Rev 238

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