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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 6563d 22h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6566d 04h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6566d 04h /
235 rev 4. mohor 6566d 18h /
234 Figure list assed to the revision 3. mohor 6567d 02h /
233 Revision 0.3 released. Some figures added. mohor 6567d 03h /
232 fpga define added. mohor 6571d 22h /
231 Description of Core Modules added (figure). mohor 6573d 23h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6577d 20h /
229 case changed to casex. mohor 6577d 20h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6578d 00h /
227 Changed BIST scan signals. tadejm 6578d 00h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6578d 01h /
225 Some minor changes. tadejm 6578d 01h /
224 Signals for a wave window in Modelsim. tadejm 6578d 02h /
223 Some code changed due to bug fixes. tadejm 6578d 03h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 6582d 00h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6582d 00h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6585d 01h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6585d 01h /

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