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Rev Log message Author Age Path
238 Defines fixed to use generic RAM by default. mohor 6456d 00h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6458d 05h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6458d 05h /
235 rev 4. mohor 6458d 20h /
234 Figure list assed to the revision 3. mohor 6459d 04h /
233 Revision 0.3 released. Some figures added. mohor 6459d 04h /
232 fpga define added. mohor 6463d 23h /
231 Description of Core Modules added (figure). mohor 6466d 00h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6469d 21h /
229 case changed to casex. mohor 6469d 21h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6470d 01h /
227 Changed BIST scan signals. tadejm 6470d 01h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6470d 02h /
225 Some minor changes. tadejm 6470d 02h /
224 Signals for a wave window in Modelsim. tadejm 6470d 04h /
223 Some code changed due to bug fixes. tadejm 6470d 04h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 6474d 02h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6474d 02h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6477d 02h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6477d 02h /

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