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238 Defines fixed to use generic RAM by default. mohor 6190d 20h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6193d 01h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6193d 01h /
235 rev 4. mohor 6193d 16h /
234 Figure list assed to the revision 3. mohor 6194d 00h /
233 Revision 0.3 released. Some figures added. mohor 6194d 00h /
232 fpga define added. mohor 6198d 19h /
231 Description of Core Modules added (figure). mohor 6200d 20h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 6204d 17h /
229 case changed to casex. mohor 6204d 17h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 6204d 21h /
227 Changed BIST scan signals. tadejm 6204d 21h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6204d 22h /
225 Some minor changes. tadejm 6204d 22h /
224 Signals for a wave window in Modelsim. tadejm 6205d 00h /
223 Some code changed due to bug fixes. tadejm 6205d 00h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 6208d 22h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6208d 22h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 6211d 22h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6211d 22h /

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