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238 Defines fixed to use generic RAM by default. mohor 7395d 07h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7397d 12h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7397d 12h /
235 rev 4. mohor 7398d 03h /
234 Figure list assed to the revision 3. mohor 7398d 11h /
233 Revision 0.3 released. Some figures added. mohor 7398d 11h /
232 fpga define added. mohor 7403d 06h /
231 Description of Core Modules added (figure). mohor 7405d 07h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7409d 04h /
229 case changed to casex. mohor 7409d 04h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7409d 08h /
227 Changed BIST scan signals. tadejm 7409d 08h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7409d 09h /
225 Some minor changes. tadejm 7409d 09h /
224 Signals for a wave window in Modelsim. tadejm 7409d 11h /
223 Some code changed due to bug fixes. tadejm 7409d 11h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7413d 09h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7413d 09h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7416d 09h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 7416d 09h /

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