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242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7163d 21h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7163d 21h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7163d 21h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7163d 21h /
238 Defines fixed to use generic RAM by default. mohor 7176d 01h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7178d 07h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7178d 07h /
235 rev 4. mohor 7178d 21h /
234 Figure list assed to the revision 3. mohor 7179d 05h /
233 Revision 0.3 released. Some figures added. mohor 7179d 06h /
232 fpga define added. mohor 7184d 01h /
231 Description of Core Modules added (figure). mohor 7186d 02h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7189d 23h /
229 case changed to casex. mohor 7189d 23h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7190d 02h /
227 Changed BIST scan signals. tadejm 7190d 02h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7190d 04h /
225 Some minor changes. tadejm 7190d 04h /
224 Signals for a wave window in Modelsim. tadejm 7190d 05h /
223 Some code changed due to bug fixes. tadejm 7190d 05h /

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