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Rev Log message Author Age Path
243 Late collision is not reported any more. tadejm 7439d 15h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).
tadejm 7440d 05h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.
tadejm 7440d 05h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7440d 05h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.
tadejm 7440d 05h /
238 Defines fixed to use generic RAM by default. mohor 7452d 09h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7454d 15h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7454d 15h /
235 rev 4. mohor 7455d 05h /
234 Figure list assed to the revision 3. mohor 7455d 14h /
233 Revision 0.3 released. Some figures added. mohor 7455d 14h /
232 fpga define added. mohor 7460d 09h /
231 Description of Core Modules added (figure). mohor 7462d 10h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7466d 07h /
229 case changed to casex. mohor 7466d 07h /
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7466d 11h /
227 Changed BIST scan signals. tadejm 7466d 11h /
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7466d 12h /
225 Some minor changes. tadejm 7466d 12h /
224 Signals for a wave window in Modelsim. tadejm 7466d 14h /
223 Some code changed due to bug fixes. tadejm 7466d 14h /
222 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7470d 12h /
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7470d 12h /
220 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7473d 12h /
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7473d 12h /
218 Typo error fixed. (When using Bist) mohor 7473d 14h /
217 Bist supported. mohor 7473d 14h /
216 Bist signals added. mohor 7473d 14h /
215 Bist supported. mohor 7473d 15h /
214 Signals for WISHBONE B3 compliant interface added. mohor 7474d 11h /

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