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248 wb_rst_i is used for MIIM reset. mohor 7836d 11h /
247 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7839d 14h /
246 Since r_Rst bit is not used any more, default value is changed to 0xa000. mohor 7839d 14h /
245 Rev 1.7. mohor 7840d 08h /
244 r_Rst signal does not reset any module any more and is removed from the design. mohor 7840d 10h /
243 Late collision is not reported any more. tadejm 7840d 16h /
242 Late collision is reported only when not in the full duplex.
Sample is taken (for status) as soon as MRxDV is not valid (regardless
of the received byte cnt).		 tadejm 7841d 06h /
241 StartIdle state changed (not important the size of the packet).
StartData1 activates only while ByteCnt is smaller than the MaxFrame.		 tadejm 7841d 06h /
240 All modules are reset with wb_rst instead of the r_Rst. Exception is MII module. tadejm 7841d 06h /
239 RxError is not generated when small frame reception is enabled and small
frames are received.		 tadejm 7841d 06h /
238 Defines fixed to use generic RAM by default. mohor 7853d 10h /
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7855d 16h /
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7855d 16h /
235 rev 4. mohor 7856d 06h /
234 Figure list assed to the revision 3. mohor 7856d 15h /
233 Revision 0.3 released. Some figures added. mohor 7856d 15h /
232 fpga define added. mohor 7861d 10h /
231 Description of Core Modules added (figure). mohor 7863d 11h /
230 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7867d 08h /
229 case changed to casex. mohor 7867d 08h /

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