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27 File names changed to lower case. mohor 6842d 23h /
26 First release of product brief. mohor 6843d 00h /
25 First release of product brief. mohor 6843d 00h /
24 Log file added. mohor 6865d 11h /
23 Number of addresses (wb_adr_i) minimized. mohor 6865d 11h /
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 6865d 14h /
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 6866d 10h /
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 6890d 07h /
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 6890d 07h /
18 Few little NCSIM warnings fixed. mohor 6903d 08h /
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 6930d 08h /
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 6937d 14h /
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 6939d 08h /
14 Unconnected signals are now connected. mohor 6943d 13h /
13 New directory structure. Files upodated and put together. mohor 6945d 22h /
12 Directory structure changed. Files checked and joind together. mohor 6946d 01h /
11 Directory structure changed. Files checked and joind together. mohor 6946d 01h /
10 Directory structure changed. Files checked and joind together. mohor 6946d 01h /
9 Documentation updated to be synchronized to the verilog files. mohor 6973d 09h /
8 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.
mohor 7000d 14h /

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