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31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 7519d 06h /
30 BD section updated. mohor 7521d 03h /
29 Generic memory model is used. Defines are changed for the same reason. mohor 7541d 01h /
28 New release. Name changed to lower case. mohor 7543d 17h /
27 File names changed to lower case. mohor 7543d 17h /
26 First release of product brief. mohor 7543d 17h /
25 First release of product brief. mohor 7543d 17h /
24 Log file added. mohor 7566d 04h /
23 Number of addresses (wb_adr_i) minimized. mohor 7566d 04h /
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7566d 07h /
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 7567d 04h /
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 7591d 01h /
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 7591d 01h /
18 Few little NCSIM warnings fixed. mohor 7604d 02h /
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 7631d 02h /
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 7638d 07h /
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 7640d 01h /
14 Unconnected signals are now connected. mohor 7644d 06h /
13 New directory structure. Files upodated and put together. mohor 7646d 15h /
12 Directory structure changed. Files checked and joind together. mohor 7646d 18h /
11 Directory structure changed. Files checked and joind together. mohor 7646d 18h /
10 Directory structure changed. Files checked and joind together. mohor 7646d 18h /
9 Documentation updated to be synchronized to the verilog files. mohor 7674d 03h /
8 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.
mohor 7701d 08h /
7 Version 1.3. Status registers added. DMA channels 2 and 3 are not used
any more. Things that are implementation specific were deleted out of the
document.
mohor 7701d 08h /
6 no message mohor 7701d 08h /
5 This is a Microsoft version of the spec in the pdf format. mohor 7705d 17h /
4 deleted mohor 7705d 17h /
3 This commit was manufactured by cvs2svn to create tag 'arelease'. 7777d 18h /
2 no message mohor 7777d 18h /

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