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Rev Log message Author Age Path
310 More signals. tadejm 5927d 00h /
309 Update file list files for different RAM models with byte select accessing. tadejm 5927d 00h /
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 5927d 00h /
307 This commit was manufactured by cvs2svn to create tag 'rel_24'. 5927d 22h /
306 Lapsus fixed (!we -> ~we). simons 5927d 22h /
305 This commit was manufactured by cvs2svn to create tag 'rel_23'. 5949d 19h /
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 5949d 19h /
303 This commit was manufactured by cvs2svn to create tag 'rel_22'. 5976d 05h /
302 mbist signals updated according to newest convention markom 5976d 05h /
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 5986d 21h /
300 This commit was manufactured by cvs2svn to create tag 'rel_21'. 6034d 01h /
299 Artisan RAMs added. mohor 6034d 01h /
298 This commit was manufactured by cvs2svn to create tag 'rel_20'. 6039d 20h /
297 Artisan ram instance added. simons 6039d 20h /
296 This commit was manufactured by cvs2svn to create tag 'rel_19'. 6040d 23h /
295 Few minor changes. tadejm 6040d 23h /
294 Added path to a file with distributed RAM instances for xilinx. tadejm 6043d 00h /
293 initial. tadejm 6066d 21h /
292 Corrected mistake. tadejm 6066d 21h /
291 initial tadejm 6066d 22h /

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