OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 317

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 7350d 12h /
316 This commit was manufactured by cvs2svn to create tag 'rel_25'. 7453d 09h /
315 Updated testbench. Some more testcases, some repaired. tadejm 7453d 09h /
314 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7453d 09h /
313 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7453d 09h /
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 7453d 09h /
311 Update script for running different file list files for different RAM models. tadejm 7453d 09h /
310 More signals. tadejm 7453d 09h /
309 Update file list files for different RAM models with byte select accessing. tadejm 7453d 09h /
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 7453d 09h /
307 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7454d 07h /
306 Lapsus fixed (!we -> ~we). simons 7454d 07h /
305 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7476d 03h /
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 7476d 03h /
303 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7502d 14h /
302 mbist signals updated according to newest convention markom 7502d 14h /
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 7513d 06h /
300 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7560d 09h /
299 Artisan RAMs added. mohor 7560d 09h /
298 This commit was manufactured by cvs2svn to create tag 'rel_20'. 7566d 05h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.