OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 317

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
317 Multicast detection fixed. Only the LSB of the first byte is checked. igorm 5692d 22h /
316 This commit was manufactured by cvs2svn to create tag 'rel_25'. 5795d 19h /
315 Updated testbench. Some more testcases, some repaired. tadejm 5795d 19h /
314 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 5795d 19h /
313 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 5795d 19h /
312 Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. tadejm 5795d 19h /
311 Update script for running different file list files for different RAM models. tadejm 5795d 19h /
310 More signals. tadejm 5795d 19h /
309 Update file list files for different RAM models with byte select accessing. tadejm 5795d 19h /
308 Moved RAM model file path from sim_file_list.lst to this file. tadejm 5795d 19h /
307 This commit was manufactured by cvs2svn to create tag 'rel_24'. 5796d 17h /
306 Lapsus fixed (!we -> ~we). simons 5796d 17h /
305 This commit was manufactured by cvs2svn to create tag 'rel_23'. 5818d 14h /
304 WISHBONE slave changed and tested from only 32-bit accesss to byte access. tadejm 5818d 14h /
303 This commit was manufactured by cvs2svn to create tag 'rel_22'. 5845d 00h /
302 mbist signals updated according to newest convention markom 5845d 00h /
301 Update RxEnSync only when mrxdv_pad_i is inactive (LOW). knguyen 5855d 16h /
300 This commit was manufactured by cvs2svn to create tag 'rel_21'. 5902d 20h /
299 Artisan RAMs added. mohor 5902d 20h /
298 This commit was manufactured by cvs2svn to create tag 'rel_20'. 5908d 15h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.