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Rev Log message Author Age Path
347 Added information about running with Icarus Verilog olof 4744d 23h /
346 Updated project location olof 4745d 01h /
345 Temporarily disable failing tests olof 4745d 02h /
344 bit 9 in phy control register is self clearing olof 4751d 04h /
343 Address miss should not be asserted on short frames olof 4755d 00h /
342 Added cast to avoid inequality when comparing different data types olof 4755d 01h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4755d 01h /
340 Don't fail if log dir already exists olof 4755d 22h /
339 Added basic support for Icarus Verilog olof 4756d 22h /
338 root 5549d 03h /
337 root 5605d 05h /
336 Added old uploaded documents to new repository. root 5606d 08h /
335 New directory structure. root 5606d 08h /
334 Minor fixes for Icarus simulator. igorm 7054d 11h /
333 Some small fixes + some troubles fixed. igorm 7054d 22h /
332 Case statement improved for synthesys. igorm 7068d 04h /
331 Tests for delayed CRC and defer indication added. igorm 7083d 05h /
330 Warning fixes. igorm 7083d 06h /
329 Defer indication fixed. igorm 7083d 07h /
328 Delayed CRC fixed. igorm 7083d 07h /

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