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Rev Log message Author Age Path
349 Make all parameters configurable from top level olof 4605d 22h /
348 Added option to dump VCD files olof 4606d 21h /
347 Added information about running with Icarus Verilog olof 4606d 22h /
346 Updated project location olof 4607d 00h /
345 Temporarily disable failing tests olof 4607d 02h /
344 bit 9 in phy control register is self clearing olof 4613d 04h /
343 Address miss should not be asserted on short frames olof 4617d 00h /
342 Added cast to avoid inequality when comparing different data types olof 4617d 00h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4617d 00h /
340 Don't fail if log dir already exists olof 4617d 21h /
339 Added basic support for Icarus Verilog olof 4618d 21h /
338 root 5411d 02h /
337 root 5467d 04h /
336 Added old uploaded documents to new repository. root 5468d 08h /
335 New directory structure. root 5468d 08h /
334 Minor fixes for Icarus simulator. igorm 6916d 10h /
333 Some small fixes + some troubles fixed. igorm 6916d 22h /
332 Case statement improved for synthesys. igorm 6930d 03h /
331 Tests for delayed CRC and defer indication added. igorm 6945d 05h /
330 Warning fixes. igorm 6945d 05h /

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