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Rev Log message Author Age Path
349 Make all parameters configurable from top level olof 4635d 13h /
348 Added option to dump VCD files olof 4636d 12h /
347 Added information about running with Icarus Verilog olof 4636d 13h /
346 Updated project location olof 4636d 15h /
345 Temporarily disable failing tests olof 4636d 16h /
344 bit 9 in phy control register is self clearing olof 4642d 18h /
343 Address miss should not be asserted on short frames olof 4646d 14h /
342 Added cast to avoid inequality when comparing different data types olof 4646d 14h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4646d 15h /
340 Don't fail if log dir already exists olof 4647d 12h /
339 Added basic support for Icarus Verilog olof 4648d 11h /
338 root 5440d 17h /
337 root 5496d 19h /
336 Added old uploaded documents to new repository. root 5497d 22h /
335 New directory structure. root 5497d 22h /
334 Minor fixes for Icarus simulator. igorm 6946d 00h /
333 Some small fixes + some troubles fixed. igorm 6946d 12h /
332 Case statement improved for synthesys. igorm 6959d 18h /
331 Tests for delayed CRC and defer indication added. igorm 6974d 19h /
330 Warning fixes. igorm 6974d 20h /

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