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Rev Log message Author Age Path
349 Make all parameters configurable from top level olof 4695d 07h /
348 Added option to dump VCD files olof 4696d 06h /
347 Added information about running with Icarus Verilog olof 4696d 07h /
346 Updated project location olof 4696d 09h /
345 Temporarily disable failing tests olof 4696d 10h /
344 bit 9 in phy control register is self clearing olof 4702d 12h /
343 Address miss should not be asserted on short frames olof 4706d 08h /
342 Added cast to avoid inequality when comparing different data types olof 4706d 08h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4706d 09h /
340 Don't fail if log dir already exists olof 4707d 06h /
339 Added basic support for Icarus Verilog olof 4708d 05h /
338 root 5500d 11h /
337 root 5556d 13h /
336 Added old uploaded documents to new repository. root 5557d 16h /
335 New directory structure. root 5557d 16h /
334 Minor fixes for Icarus simulator. igorm 7005d 18h /
333 Some small fixes + some troubles fixed. igorm 7006d 06h /
332 Case statement improved for synthesys. igorm 7019d 12h /
331 Tests for delayed CRC and defer indication added. igorm 7034d 13h /
330 Warning fixes. igorm 7034d 14h /

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