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35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8357d 23h /
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8358d 00h /
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8358d 04h /
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8358d 04h /
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8358d 05h /
30 BD section updated. mohor 8360d 01h /
29 Generic memory model is used. Defines are changed for the same reason. mohor 8380d 00h /
28 New release. Name changed to lower case. mohor 8382d 16h /
27 File names changed to lower case. mohor 8382d 16h /
26 First release of product brief. mohor 8382d 16h /
25 First release of product brief. mohor 8382d 16h /
24 Log file added. mohor 8405d 03h /
23 Number of addresses (wb_adr_i) minimized. mohor 8405d 03h /
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8405d 06h /
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8406d 02h /
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8430d 00h /
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8430d 00h /
18 Few little NCSIM warnings fixed. mohor 8443d 00h /
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8470d 00h /
16 "else" was missing within the always block in file eth_wishbonedma.v. mohor 8477d 06h /

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