URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 35

Rev	Log message	Author	Age	Path
15	A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). Include files fixed to contain no path. File names and module names changed ta have a eth_ prologue in the name. File eth_timescale.v is used to define timescale All pin names on the top module are changed to contain _I, _O or _OE at the end. Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O and Mdo_OE. The bidirectional signal must be created on the top level. This is done due to the ASIC tools.	mohor	8320d 05h	/
14	Unconnected signals are now connected.	mohor	8324d 10h	/
13	New directory structure. Files upodated and put together.	mohor	8326d 19h	/
12	Directory structure changed. Files checked and joind together.	mohor	8326d 22h	/
11	Directory structure changed. Files checked and joind together.	mohor	8326d 22h	/
10	Directory structure changed. Files checked and joind together.	mohor	8326d 22h	/
9	Documentation updated to be synchronized to the verilog files.	mohor	8354d 07h	/
8	Version 1.3. Status registers added. DMA channels 2 and 3 are not used any more. Things that are implementation specific were deleted out of the document.	mohor	8381d 12h	/
7	Version 1.3. Status registers added. DMA channels 2 and 3 are not used any more. Things that are implementation specific were deleted out of the document.	mohor	8381d 12h	/
6	no message	mohor	8381d 12h	/