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Rev Log message Author Age Path
355 Import Julius Baxter's verilator hints from ORPSoC olof 3938d 11h /
354 Whitespace cleanup olof 3938d 11h /
353 Inherit fixes for bit width of constants from ORPSoC olof 3940d 13h /
352 Removed delayed assignments from rtl code olof 3944d 19h /
351 Turn defines into parameters in eth_cop olof 3953d 08h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3953d 09h /
349 Make all parameters configurable from top level olof 3954d 10h /
348 Added option to dump VCD files olof 3955d 09h /
347 Added information about running with Icarus Verilog olof 3955d 09h /
346 Updated project location olof 3955d 11h /
345 Temporarily disable failing tests olof 3955d 13h /
344 bit 9 in phy control register is self clearing olof 3961d 15h /
343 Address miss should not be asserted on short frames olof 3965d 11h /
342 Added cast to avoid inequality when comparing different data types olof 3965d 11h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3965d 11h /
340 Don't fail if log dir already exists olof 3966d 09h /
339 Added basic support for Icarus Verilog olof 3967d 08h /
338 root 4759d 14h /
337 root 4815d 16h /
336 Added old uploaded documents to new repository. root 4816d 19h /

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