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Rev Log message Author Age Path
355 Import Julius Baxter's verilator hints from ORPSoC olof 4682d 19h /
354 Whitespace cleanup olof 4682d 20h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4684d 21h /
352 Removed delayed assignments from rtl code olof 4689d 03h /
351 Turn defines into parameters in eth_cop olof 4697d 17h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4697d 18h /
349 Make all parameters configurable from top level olof 4698d 18h /
348 Added option to dump VCD files olof 4699d 17h /
347 Added information about running with Icarus Verilog olof 4699d 18h /
346 Updated project location olof 4699d 20h /
345 Temporarily disable failing tests olof 4699d 21h /
344 bit 9 in phy control register is self clearing olof 4705d 23h /
343 Address miss should not be asserted on short frames olof 4709d 19h /
342 Added cast to avoid inequality when comparing different data types olof 4709d 20h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4709d 20h /
340 Don't fail if log dir already exists olof 4710d 17h /
339 Added basic support for Icarus Verilog olof 4711d 17h /
338 root 5503d 22h /
337 root 5560d 00h /
336 Added old uploaded documents to new repository. root 5561d 03h /

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