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Rev Log message Author Age Path
355 Import Julius Baxter's verilator hints from ORPSoC olof 4315d 02h /
354 Whitespace cleanup olof 4315d 03h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4317d 04h /
352 Removed delayed assignments from rtl code olof 4321d 10h /
351 Turn defines into parameters in eth_cop olof 4330d 00h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4330d 00h /
349 Make all parameters configurable from top level olof 4331d 01h /
348 Added option to dump VCD files olof 4332d 00h /
347 Added information about running with Icarus Verilog olof 4332d 01h /
346 Updated project location olof 4332d 03h /
345 Temporarily disable failing tests olof 4332d 04h /
344 bit 9 in phy control register is self clearing olof 4338d 06h /
343 Address miss should not be asserted on short frames olof 4342d 02h /
342 Added cast to avoid inequality when comparing different data types olof 4342d 02h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4342d 03h /
340 Don't fail if log dir already exists olof 4343d 00h /
339 Added basic support for Icarus Verilog olof 4343d 23h /
338 root 5136d 05h /
337 root 5192d 07h /
336 Added old uploaded documents to new repository. root 5193d 10h /

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