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Rev Log message Author Age Path
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4431d 23h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4432d 00h /
354 Whitespace cleanup olof 4432d 00h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4434d 01h /
352 Removed delayed assignments from rtl code olof 4438d 07h /
351 Turn defines into parameters in eth_cop olof 4446d 21h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4446d 22h /
349 Make all parameters configurable from top level olof 4447d 22h /
348 Added option to dump VCD files olof 4448d 21h /
347 Added information about running with Icarus Verilog olof 4448d 22h /
346 Updated project location olof 4449d 00h /
345 Temporarily disable failing tests olof 4449d 02h /
344 bit 9 in phy control register is self clearing olof 4455d 04h /
343 Address miss should not be asserted on short frames olof 4459d 00h /
342 Added cast to avoid inequality when comparing different data types olof 4459d 00h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4459d 00h /
340 Don't fail if log dir already exists olof 4459d 21h /
339 Added basic support for Icarus Verilog olof 4460d 21h /
338 root 5253d 02h /
337 root 5309d 04h /

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