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Rev Log message Author Age Path
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4619d 15h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4619d 17h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4619d 18h /
354 Whitespace cleanup olof 4619d 18h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4621d 19h /
352 Removed delayed assignments from rtl code olof 4626d 01h /
351 Turn defines into parameters in eth_cop olof 4634d 15h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4634d 16h /
349 Make all parameters configurable from top level olof 4635d 16h /
348 Added option to dump VCD files olof 4636d 15h /
347 Added information about running with Icarus Verilog olof 4636d 16h /
346 Updated project location olof 4636d 18h /
345 Temporarily disable failing tests olof 4636d 20h /
344 bit 9 in phy control register is self clearing olof 4642d 22h /
343 Address miss should not be asserted on short frames olof 4646d 18h /
342 Added cast to avoid inequality when comparing different data types olof 4646d 18h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4646d 18h /
340 Don't fail if log dir already exists olof 4647d 15h /
339 Added basic support for Icarus Verilog olof 4648d 15h /
338 root 5440d 20h /

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