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Rev Log message Author Age Path
359 Verilator linting fixes olof 3947d 06h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3948d 20h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3948d 20h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3948d 22h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 3948d 22h /
354 Whitespace cleanup olof 3948d 23h /
353 Inherit fixes for bit width of constants from ORPSoC olof 3951d 00h /
352 Removed delayed assignments from rtl code olof 3955d 06h /
351 Turn defines into parameters in eth_cop olof 3963d 20h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3963d 21h /
349 Make all parameters configurable from top level olof 3964d 21h /
348 Added option to dump VCD files olof 3965d 20h /
347 Added information about running with Icarus Verilog olof 3965d 21h /
346 Updated project location olof 3965d 23h /
345 Temporarily disable failing tests olof 3966d 00h /
344 bit 9 in phy control register is self clearing olof 3972d 03h /
343 Address miss should not be asserted on short frames olof 3975d 22h /
342 Added cast to avoid inequality when comparing different data types olof 3975d 23h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3975d 23h /
340 Don't fail if log dir already exists olof 3976d 20h /

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