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Rev Log message Author Age Path
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8175d 03h /
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8178d 01h /
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8178d 01h /
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8178d 05h /
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8178d 06h /
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8178d 06h /
30 BD section updated. mohor 8180d 03h /
29 Generic memory model is used. Defines are changed for the same reason. mohor 8200d 02h /
28 New release. Name changed to lower case. mohor 8202d 17h /
27 File names changed to lower case. mohor 8202d 17h /
26 First release of product brief. mohor 8202d 17h /
25 First release of product brief. mohor 8202d 17h /
24 Log file added. mohor 8225d 04h /
23 Number of addresses (wb_adr_i) minimized. mohor 8225d 05h /
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8225d 07h /
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8226d 04h /
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8250d 01h /
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8250d 01h /
18 Few little NCSIM warnings fixed. mohor 8263d 02h /
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 8290d 02h /

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