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Rev Log message Author Age Path
361 created branch unneback unneback 4790d 09h /
360 Added partial implementation of the debug register from ORPSoC olof 4791d 08h /
359 Verilator linting fixes olof 4793d 10h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4795d 00h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4795d 00h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4795d 02h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4795d 03h /
354 Whitespace cleanup olof 4795d 03h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4797d 05h /
352 Removed delayed assignments from rtl code olof 4801d 10h /
351 Turn defines into parameters in eth_cop olof 4810d 00h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4810d 01h /
349 Make all parameters configurable from top level olof 4811d 01h /
348 Added option to dump VCD files olof 4812d 00h /
347 Added information about running with Icarus Verilog olof 4812d 01h /
346 Updated project location olof 4812d 03h /
345 Temporarily disable failing tests olof 4812d 05h /
344 bit 9 in phy control register is self clearing olof 4818d 07h /
343 Address miss should not be asserted on short frames olof 4822d 03h /
342 Added cast to avoid inequality when comparing different data types olof 4822d 03h /

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