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Rev Log message Author Age Path
361 created branch unneback unneback 3941d 10h /
360 Added partial implementation of the debug register from ORPSoC olof 3942d 09h /
359 Verilator linting fixes olof 3944d 11h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3946d 01h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3946d 01h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3946d 03h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 3946d 04h /
354 Whitespace cleanup olof 3946d 04h /
353 Inherit fixes for bit width of constants from ORPSoC olof 3948d 06h /
352 Removed delayed assignments from rtl code olof 3952d 12h /
351 Turn defines into parameters in eth_cop olof 3961d 02h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3961d 02h /
349 Make all parameters configurable from top level olof 3962d 03h /
348 Added option to dump VCD files olof 3963d 02h /
347 Added information about running with Icarus Verilog olof 3963d 03h /
346 Updated project location olof 3963d 05h /
345 Temporarily disable failing tests olof 3963d 06h /
344 bit 9 in phy control register is self clearing olof 3969d 08h /
343 Address miss should not be asserted on short frames olof 3973d 04h /
342 Added cast to avoid inequality when comparing different data types olof 3973d 04h /

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