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Rev Log message Author Age Path
361 created branch unneback unneback 4656d 10h /
360 Added partial implementation of the debug register from ORPSoC olof 4657d 09h /
359 Verilator linting fixes olof 4659d 11h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4661d 01h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4661d 01h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4661d 03h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4661d 04h /
354 Whitespace cleanup olof 4661d 04h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4663d 06h /
352 Removed delayed assignments from rtl code olof 4667d 12h /
351 Turn defines into parameters in eth_cop olof 4676d 01h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4676d 02h /
349 Make all parameters configurable from top level olof 4677d 03h /
348 Added option to dump VCD files olof 4678d 02h /
347 Added information about running with Icarus Verilog olof 4678d 02h /
346 Updated project location olof 4678d 04h /
345 Temporarily disable failing tests olof 4678d 06h /
344 bit 9 in phy control register is self clearing olof 4684d 08h /
343 Address miss should not be asserted on short frames olof 4688d 04h /
342 Added cast to avoid inequality when comparing different data types olof 4688d 04h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4688d 04h /
340 Don't fail if log dir already exists olof 4689d 02h /
339 Added basic support for Icarus Verilog olof 4690d 01h /
338 root 5482d 07h /
337 root 5538d 09h /
336 Added old uploaded documents to new repository. root 5539d 12h /
335 New directory structure. root 5539d 12h /
334 Minor fixes for Icarus simulator. igorm 6987d 14h /
333 Some small fixes + some troubles fixed. igorm 6988d 02h /
332 Case statement improved for synthesys. igorm 7001d 07h /

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