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Rev Log message Author Age Path
361 created branch unneback unneback 4630d 22h /
360 Added partial implementation of the debug register from ORPSoC olof 4631d 21h /
359 Verilator linting fixes olof 4633d 23h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4635d 13h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4635d 13h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4635d 15h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4635d 16h /
354 Whitespace cleanup olof 4635d 16h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4637d 18h /
352 Removed delayed assignments from rtl code olof 4641d 23h /
351 Turn defines into parameters in eth_cop olof 4650d 13h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4650d 14h /
349 Make all parameters configurable from top level olof 4651d 15h /
348 Added option to dump VCD files olof 4652d 14h /
347 Added information about running with Icarus Verilog olof 4652d 14h /
346 Updated project location olof 4652d 16h /
345 Temporarily disable failing tests olof 4652d 18h /
344 bit 9 in phy control register is self clearing olof 4658d 20h /
343 Address miss should not be asserted on short frames olof 4662d 16h /
342 Added cast to avoid inequality when comparing different data types olof 4662d 16h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4662d 16h /
340 Don't fail if log dir already exists olof 4663d 14h /
339 Added basic support for Icarus Verilog olof 4664d 13h /
338 root 5456d 19h /
337 root 5512d 21h /
336 Added old uploaded documents to new repository. root 5514d 00h /
335 New directory structure. root 5514d 00h /
334 Minor fixes for Icarus simulator. igorm 6962d 02h /
333 Some small fixes + some troubles fixed. igorm 6962d 14h /
332 Case statement improved for synthesys. igorm 6975d 19h /

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