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Rev Log message Author Age Path
363 quartus project files unneback 4699d 14h /
362 added Makefiles to build project unneback 4699d 14h /
361 created branch unneback unneback 4699d 14h /
360 Added partial implementation of the debug register from ORPSoC olof 4700d 13h /
359 Verilator linting fixes olof 4702d 15h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4704d 05h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4704d 05h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4704d 07h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4704d 08h /
354 Whitespace cleanup olof 4704d 08h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4706d 10h /
352 Removed delayed assignments from rtl code olof 4710d 16h /
351 Turn defines into parameters in eth_cop olof 4719d 05h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4719d 06h /
349 Make all parameters configurable from top level olof 4720d 07h /
348 Added option to dump VCD files olof 4721d 06h /
347 Added information about running with Icarus Verilog olof 4721d 06h /
346 Updated project location olof 4721d 08h /
345 Temporarily disable failing tests olof 4721d 10h /
344 bit 9 in phy control register is self clearing olof 4727d 12h /

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