OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 363

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
363 quartus project files unneback 3939d 05h /
362 added Makefiles to build project unneback 3939d 06h /
361 created branch unneback unneback 3939d 06h /
360 Added partial implementation of the debug register from ORPSoC olof 3940d 04h /
359 Verilator linting fixes olof 3942d 07h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3943d 21h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3943d 21h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3943d 23h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 3943d 23h /
354 Whitespace cleanup olof 3944d 00h /
353 Inherit fixes for bit width of constants from ORPSoC olof 3946d 01h /
352 Removed delayed assignments from rtl code olof 3950d 07h /
351 Turn defines into parameters in eth_cop olof 3958d 21h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3958d 22h /
349 Make all parameters configurable from top level olof 3959d 22h /
348 Added option to dump VCD files olof 3960d 21h /
347 Added information about running with Icarus Verilog olof 3960d 22h /
346 Updated project location olof 3961d 00h /
345 Temporarily disable failing tests olof 3961d 01h /
344 bit 9 in phy control register is self clearing olof 3967d 04h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.