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Rev Log message Author Age Path
363 quartus project files unneback 4669d 06h /
362 added Makefiles to build project unneback 4669d 06h /
361 created branch unneback unneback 4669d 07h /
360 Added partial implementation of the debug register from ORPSoC olof 4670d 05h /
359 Verilator linting fixes olof 4672d 07h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4673d 21h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4673d 22h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4673d 23h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4674d 00h /
354 Whitespace cleanup olof 4674d 01h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4676d 02h /
352 Removed delayed assignments from rtl code olof 4680d 08h /
351 Turn defines into parameters in eth_cop olof 4688d 22h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4688d 22h /
349 Make all parameters configurable from top level olof 4689d 23h /
348 Added option to dump VCD files olof 4690d 22h /
347 Added information about running with Icarus Verilog olof 4690d 23h /
346 Updated project location olof 4691d 01h /
345 Temporarily disable failing tests olof 4691d 02h /
344 bit 9 in phy control register is self clearing olof 4697d 04h /
343 Address miss should not be asserted on short frames olof 4701d 00h /
342 Added cast to avoid inequality when comparing different data types olof 4701d 00h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4701d 01h /
340 Don't fail if log dir already exists olof 4701d 22h /
339 Added basic support for Icarus Verilog olof 4702d 21h /
338 root 5495d 03h /
337 root 5551d 05h /
336 Added old uploaded documents to new repository. root 5552d 08h /
335 New directory structure. root 5552d 08h /
334 Minor fixes for Icarus simulator. igorm 7000d 10h /

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