OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] - Rev 366

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
366 Readded eth_top.v with a deprecation warning olof 4649d 03h /
365 Whitespace cleanup olof 4650d 02h /
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4651d 00h /
363 quartus project files unneback 4651d 08h /
362 added Makefiles to build project unneback 4651d 09h /
361 created branch unneback unneback 4651d 09h /
360 Added partial implementation of the debug register from ORPSoC olof 4652d 07h /
359 Verilator linting fixes olof 4654d 10h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4656d 00h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4656d 00h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4656d 01h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4656d 02h /
354 Whitespace cleanup olof 4656d 03h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4658d 04h /
352 Removed delayed assignments from rtl code olof 4662d 10h /
351 Turn defines into parameters in eth_cop olof 4671d 00h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4671d 01h /
349 Make all parameters configurable from top level olof 4672d 01h /
348 Added option to dump VCD files olof 4673d 00h /
347 Added information about running with Icarus Verilog olof 4673d 01h /
346 Updated project location olof 4673d 03h /
345 Temporarily disable failing tests olof 4673d 04h /
344 bit 9 in phy control register is self clearing olof 4679d 06h /
343 Address miss should not be asserted on short frames olof 4683d 02h /
342 Added cast to avoid inequality when comparing different data types olof 4683d 03h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4683d 03h /
340 Don't fail if log dir already exists olof 4684d 00h /
339 Added basic support for Icarus Verilog olof 4685d 00h /
338 root 5477d 05h /
337 root 5533d 07h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.