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Rev Log message Author Age Path
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 4527d 23h /
366 Readded eth_top.v with a deprecation warning olof 4652d 03h /
365 Whitespace cleanup olof 4653d 02h /
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4654d 00h /
363 quartus project files unneback 4654d 09h /
362 added Makefiles to build project unneback 4654d 09h /
361 created branch unneback unneback 4654d 09h /
360 Added partial implementation of the debug register from ORPSoC olof 4655d 08h /
359 Verilator linting fixes olof 4657d 10h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4659d 00h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4659d 00h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4659d 02h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4659d 03h /
354 Whitespace cleanup olof 4659d 03h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4661d 04h /
352 Removed delayed assignments from rtl code olof 4665d 10h /
351 Turn defines into parameters in eth_cop olof 4674d 00h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4674d 01h /
349 Make all parameters configurable from top level olof 4675d 01h /
348 Added option to dump VCD files olof 4676d 00h /

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