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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 3751d 01h /
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 3813d 22h /
366 Readded eth_top.v with a deprecation warning olof 3938d 02h /
365 Whitespace cleanup olof 3939d 01h /
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 3939d 23h /
363 quartus project files unneback 3940d 07h /
362 added Makefiles to build project unneback 3940d 08h /
361 created branch unneback unneback 3940d 08h /
360 Added partial implementation of the debug register from ORPSoC olof 3941d 06h /
359 Verilator linting fixes olof 3943d 09h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3944d 23h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3944d 23h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3945d 01h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 3945d 01h /
354 Whitespace cleanup olof 3945d 02h /
353 Inherit fixes for bit width of constants from ORPSoC olof 3947d 03h /
352 Removed delayed assignments from rtl code olof 3951d 09h /
351 Turn defines into parameters in eth_cop olof 3959d 23h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3960d 00h /
349 Make all parameters configurable from top level olof 3961d 00h /
348 Added option to dump VCD files olof 3961d 23h /
347 Added information about running with Icarus Verilog olof 3962d 00h /
346 Updated project location olof 3962d 02h /
345 Temporarily disable failing tests olof 3962d 04h /
344 bit 9 in phy control register is self clearing olof 3968d 06h /
343 Address miss should not be asserted on short frames olof 3972d 02h /
342 Added cast to avoid inequality when comparing different data types olof 3972d 02h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3972d 02h /
340 Don't fail if log dir already exists olof 3972d 23h /
339 Added basic support for Icarus Verilog olof 3973d 23h /

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