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37 Link in the header changed. mohor 8137d 14h /
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8183d 12h /
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8186d 10h /
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8186d 10h /
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8186d 14h /
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8186d 15h /
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8186d 15h /
30 BD section updated. mohor 8188d 12h /
29 Generic memory model is used. Defines are changed for the same reason. mohor 8208d 10h /
28 New release. Name changed to lower case. mohor 8211d 02h /
27 File names changed to lower case. mohor 8211d 02h /
26 First release of product brief. mohor 8211d 02h /
25 First release of product brief. mohor 8211d 02h /
24 Log file added. mohor 8233d 13h /
23 Number of addresses (wb_adr_i) minimized. mohor 8233d 13h /
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8233d 16h /
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8234d 13h /
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8258d 10h /
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8258d 10h /
18 Few little NCSIM warnings fixed. mohor 8271d 11h /

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