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39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.
mohor 8148d 04h /
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8157d 06h /
37 Link in the header changed. mohor 8157d 07h /
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8203d 04h /
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8206d 02h /
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8206d 02h /
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8206d 06h /
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8206d 07h /
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8206d 07h /
30 BD section updated. mohor 8208d 04h /
29 Generic memory model is used. Defines are changed for the same reason. mohor 8228d 03h /
28 New release. Name changed to lower case. mohor 8230d 18h /
27 File names changed to lower case. mohor 8230d 18h /
26 First release of product brief. mohor 8230d 18h /
25 First release of product brief. mohor 8230d 18h /
24 Log file added. mohor 8253d 05h /
23 Number of addresses (wb_adr_i) minimized. mohor 8253d 06h /
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8253d 08h /
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 8254d 05h /
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 8278d 02h /

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