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Rev	Log message	Author	Age	Path
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8114d 18h	/
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8115d 16h	/
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8119d 20h	/
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8128d 22h	/
37	Link in the header changed.	mohor	8128d 22h	/
36	TX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8174d 20h	/
35	RX_BD_NUM changed to TX_BD_NUM. Few typos corrected.	mohor	8177d 17h	/
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8177d 17h	/
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8177d 22h	/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8177d 22h	/
31	RX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8177d 22h	/
30	BD section updated.	mohor	8179d 19h	/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8199d 18h	/
28	New release. Name changed to lower case.	mohor	8202d 09h	/
27	File names changed to lower case.	mohor	8202d 09h	/
26	First release of product brief.	mohor	8202d 10h	/
25	First release of product brief.	mohor	8202d 10h	/
24	Log file added.	mohor	8224d 21h	/
23	Number of addresses (wb_adr_i) minimized.	mohor	8224d 21h	/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8225d 00h	/

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[/] - Rev 41

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