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Subversion Repositories ethmac

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Rev	Log message	Author	Age	Path
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8255d 13h	/
46	HASH0 and HASH1 registers added.	mohor	8255d 13h	/
45	Ethernet Datasheet added.	mohor	8255d 19h	/
44	Ethernet Datasheet added to cvs.	mohor	8255d 19h	/
43	Tx status is written back to the BD.	mohor	8256d 21h	/
42	Rx status is written back to the BD.	mohor	8259d 13h	/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8261d 16h	/
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8262d 13h	/
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8266d 17h	/
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8275d 19h	/
37	Link in the header changed.	mohor	8275d 19h	/
36	TX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8321d 17h	/
35	RX_BD_NUM changed to TX_BD_NUM. Few typos corrected.	mohor	8324d 15h	/
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8324d 15h	/
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8324d 19h	/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8324d 19h	/
31	RX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8324d 20h	/
30	BD section updated.	mohor	8326d 17h	/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8346d 15h	/
28	New release. Name changed to lower case.	mohor	8349d 07h	/
27	File names changed to lower case.	mohor	8349d 07h	/
26	First release of product brief.	mohor	8349d 07h	/
25	First release of product brief.	mohor	8349d 07h	/
24	Log file added.	mohor	8371d 18h	/
23	Number of addresses (wb_adr_i) minimized.	mohor	8371d 18h	/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8371d 21h	/
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8372d 18h	/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8396d 15h	/
19	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8396d 15h	/
18	Few little NCSIM warnings fixed.	mohor	8409d 16h	/

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[/] - Rev 47

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