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Rev Log message Author Age Path
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.
mohor 7283d 10h /
46 HASH0 and HASH1 registers added. mohor 7283d 10h /
45 Ethernet Datasheet added. mohor 7283d 16h /
44 Ethernet Datasheet added to cvs. mohor 7283d 16h /
43 Tx status is written back to the BD. mohor 7284d 17h /
42 Rx status is written back to the BD. mohor 7287d 10h /
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 7289d 12h /
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.
mohor 7290d 10h /
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.
mohor 7294d 14h /
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 7303d 16h /
37 Link in the header changed. mohor 7303d 16h /
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 7349d 14h /
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 7352d 11h /
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 7352d 12h /
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 7352d 16h /
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 7352d 16h /
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 7352d 17h /
30 BD section updated. mohor 7354d 13h /
29 Generic memory model is used. Defines are changed for the same reason. mohor 7374d 12h /
28 New release. Name changed to lower case. mohor 7377d 04h /
27 File names changed to lower case. mohor 7377d 04h /
26 First release of product brief. mohor 7377d 04h /
25 First release of product brief. mohor 7377d 04h /
24 Log file added. mohor 7399d 15h /
23 Number of addresses (wb_adr_i) minimized. mohor 7399d 15h /
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 7399d 18h /
21 Status signals changed, Adress decoding changed, interrupt controller
added.
mohor 7400d 14h /
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 7424d 12h /
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).
mohor 7424d 12h /
18 Few little NCSIM warnings fixed. mohor 7437d 12h /

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