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Rev Log message Author Age Path
86 Big Endian problem when sending frames fixed. mohor 8172d 20h /
85 Log info was missing. mohor 8178d 06h /
84 LinkFail signal was not latching appropriate bit. mohor 8178d 06h /
83 MAC address recognition was not correct (bytes swaped). mohor 8178d 06h /
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8178d 08h /
81 Typos fixed, INT_SOURCE and INT_MASK registers changed. mohor 8178d 08h /
80 Small fixes for external/internal DMA missmatches. mohor 8182d 10h /
79 RetryCntLatched was unused and removed from design mohor 8182d 10h /
78 WB_SEL_I was unused and removed from design mohor 8182d 10h /
77 Interrupts changed mohor 8182d 10h /
76 Interrupts changed in the top file mohor 8182d 10h /
75 r_Bro is used for accepting/denying frames mohor 8182d 11h /
74 Reset values are passed to registers through parameters mohor 8182d 11h /
73 Number of interrupts changed mohor 8182d 11h /
72 Retry is not activated when a Tx Underrun occured mohor 8186d 14h /
71 Address recognition system added. Buffer Descriptors changed. DMA section
changed. Ports changed.
mohor 8190d 15h /
70 Small fixes. mohor 8190d 16h /
69 Define missmatch fixed. mohor 8191d 13h /
68 Registered trimmed. Unused registers removed. mohor 8192d 13h /
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8192d 14h /

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